The present invention relates to semiconductor memory devices, and more particularly, to a method for fabricating semiconductor memory devices having a conductive plug connected to a capacitor.
In a semiconductor memory device, several studies have been developed to overcome the limits of refresh in a conventional dynamic random access memory (DRAM) and to achieve large capacitance by using a ferroelectric material in a capacitor. A ferroelectric random access memory (hereinafter, referred to a FeRAM) is one of the nonvolatile memory devices that can store information in turn-off state and has an operating speed comparable to that of the conventional DRAM.
Ferroelectric material having a perovskite structure or a Bi-layered perovskite structure, such as (Bi, La)4Ti3O12 (hereinafter, referred to as a BLT), SrBi2Ta2O9 (hereinafter, referred to as an SBT) or Pb(Zr, Ti)O3 (hereinafter, referred to as a PZT) is usually used to form a dielectric layer of a capacitor in a FeRAM device. The ferroelectric layer, which is employed in a nonvolatile memory device, has a dielectric constant in a range of a few hundreds to a few thousands, and has two stabilized remnant polarization(Pr) states.
The ferroelectric capacitor is connected to a silicon substrate, that is, to one junction of a transistor, through a plug in order to increase the, integration density. The plug had been formed of polysilicon. However, in case of using polysilicon, the contact resistance between the plug and the silicon substrate is increased because of the native oxide formed on the surface of the silicon substrate. Therefore, tungsten is used for forming a plug in order to overcome the demerits of polysilicon.
The lower electrode of the ferroelectric capacitor is made of Pt/IrOx/Ir on a tungsten plug for the purpose of reducing the leakage current, preventing the diffusion of oxygen and mutual diffusion of materials in upper and lower layers. The symbol xe2x80x9c/xe2x80x9d, as used herein, defines a layering of films, so that Pt/IrOx/Ir is a stacked layers in which a Pt layer is formed at the top and a Ir layer is formed at the bottom.
It is necessary to perform a high temperature thermal treatment in an ambient of oxygen for improving the characteristics of the ferroelectric layer. Therefore, it is important to maintain the stability of the bottom electrode having the stacked layer structure and to prevent the oxidation of plug during the high temperature thermal treatment for improving the reliability of the FeRAM.
The Ir layer formed at the bottom of the lower electrode has a poor adhesion with an interlayer insulating layer, such as silicon oxide, formed beneath the Ir layer. Therefore, a glue layer should be introduced between the Ir layer and the interlayer insulating layer. The glue layer is generally formed with insulator, such as Al2O3, and thus, the portion of glue layer covering the plug should be etched selectively with an additional mask.
In addition, it is generated that the problem of mutual diffusion between the tungsten plug and the Ir layer in the lower electrode having the stacked layer structure, when the high temperature thermal treatment is preformed after forming the ferroelectric capacitor on the tungsten plug, as mentioned above. In order to prevent the mutual diffusion between the tungsten plug and the Ir layer, a buried barrier structure is introduced. The buried barrier 58A structure is composed of a diffusion barrier, such as TiN or TiAlN, in a contact hole to cover the plug.
An etch process is performed to remove a portion of a tungsten layer formed in a contact hole, in order to provide a space for the buried barrier structure. However, a residue of the tungsten layer is left on sidewalls of the contact hole after the etch process. Therefore, the thermal stability of FeRAM is deteriorated by the residue.
FIGS. 1A to 1F are cross-sectional views illustrating the manufacturing method of the FeRAM according to a prior art.
Referring to FIG. 1A, the interlayer insulating layer 12 is formed over a semiconductor substrate 10 on which a field oxide layer 11 and n+ junctions 13 are formed, and the interlayer insulating layer 12 is selectively etched to form a contact hole exposing the n+ junctions 13. The semiconductor substrate 10 is a silicon layer, such as a doped polysilicon layer or a silicon layer formed by an epitaxial growth.
A Ti layer and a TiN layer is made in this order to form a TiN/Ti layer 14, and a rapid thermal process(RTP) is performed to form a titanium silicide layer 14A by inducing the reaction of silicon atoms in the semiconductor substrate 10 and the TiN/Ti layer. 14. The titanium silicide layer 14A plays a role of the ohmic contact layer. After the RTP, a TiN layer can be formed to stabilize the titanium silicide layer 14A. Thereafter, a tungsten layer 15 is formed on the TiN/Ti layer 14 to fill the contact hole, completely.
Referring to FIG. 1B, an etch process is performed to form a tungsten plug 15A in the contact hole and to expose the surface of the TiN/Ti layer 14 on the interlayer insulating layer 12. The tungsten plug 15A is over etched by a predetermined depth with the etch process, in order to make space for a diffusion barrier in the contact hole. However, the center of the tungsten plug 15A is mainly etched, therefore, a recess R is generated. Namely, the tungsten on the portion of TiN/Ti layer 14 covering sidewalls of the entrance of the contact hole is left without being etched to induce deteriorating characteristic of FeRAM.
Referring to FIG. 1C, a TiN diffusion barrier 16 is formed on the tungsten plug 15A in the contact hole and the TiN/Ti layer 14.
Referring to FIG. 1D, the TiN diffusion barrier 16 and the TiN/Ti layer 14 are polished by the chemical-mechanical polishing (CMP) until the surface of the interlayer insulating layer 12 is exposed, therefore a buried TiN diffusion barrier 16A is formed in the contact hole.
As shown in FIG. 1D, the tungsten plug 15A, is not covered with the buried TiN diffusion barrier 16A completely, because the TiN diffusion barrier 16A is formed only in the recess R. Therefore, a portion of the tungsten plug 15A, that is the residue of tungsten on the TiN/Ti layer 14 covering the sidewalls of the entrance of the contact hole, is exposed.
Referring to FIG. 1E, the glue layer 17 is formed on the interlayer insulating layer 12 surrounding the contact hole. It is needed to selectively etch the glue layer 17 to expose the TiN diffusion barrier 16A, in case of forming the glue layer 17 with insulator. The glue layer 17 is formed to improve the adhesion between the interlayer insulating layer 12 and a Ir layer to be formed on the interlayer insulating layer 12.
The tungsten plug 15A and the TiN diffusion barrier 16A are exposed and damaged during the process for selectively etching the glue layer 12. In addition, the problem of the lateral oxidation of the plug is generated in case of exposing the plug during the process for selectively etching the glue layer 12. The possibility of the lateral oxidation is increased as the integration of device is increased.
Referring to FIG. 1F, a stacked layer comprising Pt layer 20/IrOx layer 19/Ir layer 18 is formed on the TiN diffusion barrier 16A and the glue layer 17 to form the lower electrode. Then, a ferroelectric layer 21 is formed on the lower electrode and an upper electrode 22 is subsequently formed on the ferroelectric layer 21.
The TiN diffusion barrier 16A is formed to prevent mutual diffusion between the Ir layer 18 of the lower electrode and the tungsten plug 15A. However, the exposed portion of the tungsten plug 15A, that is residue of the tungsten, denoted as xe2x80x98Axe2x80x99 in FIG. 1E, on sidewalls of entrance of the contact hole is directly contacted with the Ir layer 18. Accordingly, it is impossible to prevent the mutual diffusion between the Ir layer 18 of the lower electrode completely, and the tungsten plug 15A can be oxidized during thermal treatments.
It is, therefore, an object of the present invention to provide a semiconductor memory device manufacturing method capable of preventing direct contact between a plug and a lower electrode of a capacitor.
It is, therefore, another object of the present invention to provide a semiconductor memory device manufacturing method capable of preventing the generation of the problems caused by the misalign of mask for forming a glue layer pattern between an interlayer insulating layer and the lower electrode.
In accordance with an aspect of the present invention, there is provided a method for manufacturing a semiconductor memory device, comprising the steps of: forming an insulating layer on a semiconductor substrate; forming a contact hole exposing the semiconductor substrate by selectively etching the insulating layer; forming a first diffusion barrier on the insulating layer and in the contact hole; forming a conductive layer on the first diffusion barrier; forming a conductive plug in the contact hole by removing the conductive layer until the first diffusion barrier on the insulating layer is exposed, thereby obtaining a first recess in the contact hole, wherein the first recess is surrounded by the conductive layer in the contact hole; etching the first diffusion barrier on the insulating layer thereby forming a second recess in the contact hole, wherein a portion of the conductive plug is surrounded by the second recess and the second recess is surrounded by the insulating layer; removing the portion of the conductive plug surrounded by the second recess thereby forming a third recess in the contact hole, wherein the third recess is surrounded by the insulating layer and bottom of the of the third recess expose the first diffusion barrier and the conductive plug in the contact hole; and forming a second diffusion barrier in the third recess.
In accordance with another aspect of the present invention, there is provided a method for manufacturing a semiconductor memory device, comprising the steps of: forming an insulating layer on a semiconductor substrate; forming an adhesion layer on the insulating layer; forming a capping layer on the adhesion layer; forming a contact hole exposing the semiconductor substrate by selectively etching the capping layer, the adhesion layer and the insulating layer; forming a first diffusion barrier on the capping layer and in the contact hole; forming a conductive layer on the first diffusion barrier; forming a conductive plug in the contact hole by removing the conductive layer until the first diffusion barrier on the insulating layer is exposed, thereby obtaining a first recess in the contact hole, wherein the first recess is surrounded by the conductive layer in the contact hole; etching the first diffusion barrier on the capping layer thereby forming a second recess in the contact hole, wherein a portion of the conductive plug is surrounded by the second recess and the second recess is surrounded by the capping layer, adhesion layer and the insulating layer; removing the portion of the conductive plug surrounded by the second recess thereby forming a third recess in the contact hole, wherein the third recess is surrounded by the capping layer, adhesion layer and the insulating layer and bottom of the third recess expose the first diffusion barrier and the conductive plug in the contact hole; and forming a second diffusion barrier in the third recess and removing the capping layer on the adhesion layer.